1. Field of the Invention
An object of the present invention is a method and apparatus for the use, in a network, of a fuzzy logic processor as well as a fuzzy logic processor. The invention is aimed at simplifying the relationship among fuzzy logic processors whose use in local mode is known, with network distributed devices of great utility.
2. Discussion of the Related Art
In a system including network-distributed devices, it is possible to consider each of the devices connected to this system as a resource (an actuator) or as a source of usable information. In the field of home automation systems, different types of networks are known. In particular, these are the systems called HS (HOME SYSTEM) Batibus, CAN etc. The principle of operation of these networks lies in the use of a protocol. Each message that is transmitted on the network has a preamble, a header, a source address, a destination address, a control register, data elements and an acknowledgment or an error correction field.
The preamble generally has an indicator representing the beginning of the message. This indicator, which is used most importantly for synchronization and is known as "START", may take a variety of forms. For example, in a four-wire bus where two wires are used for the transmission of the data and two other wires are used for the transmission of a clock and electrical supply signal, an indicator START is detected by a transition on the two data wires when the clock is at a low level. In carrier current circuits, it may be a signal at a typical modulation frequency. Other conventions are applicable for the different networks.
By way of example, FIG. 3 shows an exemplary message sent on a network. In the arbitrary example shown, the message will have a 256-byte frame. In these 256 bytes, 128 first bytes correspond to a logistical part of the message. It is however possible to define a protocol that consumes fewer bytes, with for example only eleven bytes. As shown in FIG. 3, there is one byte for the preamble, 15 bytes for the header, 16 bytes for the source address and for the destination address and 80 bytes for the control register. It is possible to have only one byte for the header and the addresses and even any intermediate length or a length greater than the 1-15 byte interval. The 128 other bytes are used to transmit data elements.
FIG. 2 gives a schematic view of a network R in which three actuator devices, one ventilator, one heating radiator and one electrical domestic appliance, are connected to the network. Furthermore, detectors or control buttons a to d are connected to the network R. The network R may be of the twisted pair, carrier current, infrared, radioelectrical or other type.
Since all of the devices are connected to the same network R, it is necessary to provide each of them with an interface capable of interpreting the logistical bytes to extract data bytes so that their processing is done. U.S. Pat. Nos. 5,537,651 and 5,535,344 describe interface circuits that have to be fitted into each device, especially the actuator devices, such as the ventilator, the heating radiator and the domestic electrical appliance in order to make them understand the messages that are transmitted on the network R.
A known interface uses a local sequencer to control routing operations in the network by reading received messages. The problem of this technique is the cost and complexity of the required processor. Indeed, the extent to which a fuzzy logic processor is capable of managing complex situations at little cost depends on the extent to which it can receive, in a simple way, the data that it has to process. To simplify matters, a fuzzy logic processor currently available on the market, for example W A R P 1, W A R P 2 or W A R P 3, by SGS-THOMSON MICROELECTRONICS, has at least eight inputs for the data elements and two outputs for the commands, all for a price of less than 10 francs, namely 2 dollars. The making of an interface such as the one described in the above-mentioned patent applications has a cost of the same order. This means that making a fuzzy logic processor which can be used in a network presently costs twice as much as it should. Furthermore, it is complex to develop.
In an embodiment of the present invention, this problem of cost and complexity will be resolved through the use of a fuzzy logic processor to perform the functions of the local sequencer. The local sequencer must in practice be a processor. A fuzzy logic processor is not normally designed, by virtue of its specific operation, to behave like a normal processor. This specific feature shall be explained further below. It may be recalled that a normal processor has a register of instructions and one or more data input/output registers. The processor consists of an arrangement of logic gates that receive these data elements as input. These gates are validated as a function of an instruction code present in the instruction register. An operation of this kind is not available as such in a fuzzy logic processor.